1. Field of the Invention
The invention relates in general to a method of driving a liquid crystal display panel, and more particularly to a method of driving a liquid crystal display panel having dual thin-film-transistor pixels.
2. Description of the Related Art
Referring to FIG. 1, an equivalent circuit diagram of part of the pixels of a conventional liquid crystal display panel is shown. In FIG. 1, for pixels in the same row, every two adjacent pixels share one data line. Take the left pixel LP (m, n) and the right pixel RP (m, n) of FIG. 1 for example. The two pixels, coupled to a scan line Sm+1 and a data line Dn, are respectively positioned at the two sides of the data line Dn, and are referred as the left pixel LP (m, n) and the right pixel RP (m, n) hereafter.
The right pixel RP (m, n) is controlled by a thin film transistor M21 and a thin film transistor M22. The gate of the thin film transistor M21 is electrically connected to the scan line Sm+1, while the source of the thin film transistor M21 is electrically connected to the data line Dn. The gate of the thin film transistor M22 is electrically connected to a scan line Sm+2, while the source of the thin film transistor M22 is electrically connected to the thin film transistor M21. The left pixel LP (m, n) is controlled by a thin film transistor M11 and a thin film transistor M12. The gate of the thin film transistor M11 is electrically connected to the scan line Sm+1, while the source of the thin film transistor M11 is electrically connected to the data line Dn. The gate of the thin film transistor M12 is electrically connected to the scan line Sm, while the source of the thin film transistor M12 is electrically connected to the drain of the thin film transistor M11. The pixels on the display panel can be divided into two categories, namely, the left pixels LP and the right pixels RP, according to the position of the pixel with respect to the data line.
Referring to FIG. 2, a timing diagram of the scan signals of the scan lines Sm, Sm+1 and Sm+2 of the circuit of FIG. 1 is shown. The scanning of the pixels in each row can be divided into two phases of sub-scanning. The first sub-scanning scans all left pixels LP in a row, while the second sub-scanning scans all right pixels RP in the row. For example, when the pixels in the mth row are scanned, at first, during a first time period T1, the scan lines Sm and Sm+1 are enabled at the same time, meanwhile, the thin film transistors M11 and M12 are turned on at the same time, so a pixel voltage is inputted to the left pixel LP (m, n) via the data line Dn. Thus, the first sub-scanning is completed. Then, during a second time period T2, the second sub-scanning is performed. The scan lines Sm+1 and Sm+2 are enabled, meanwhile, the thin film transistors M21 and M22 are turned on, so a pixel voltage is inputted to the right pixel RP (m, n) via the data line Dn.
Since each pixel has dual thin film transistors, the aperture ratio will be lower than a pixel having one thin film transistor. In order to increase the aperture ratio, another pixel configuration is provided. Referring to FIG. 3, an equivalent circuit diagram of part of the pixels of another conventional liquid crystal display panel is shown. Take the left pixel LP (m, n) and the right pixel RP (m, n) of FIG. 3 for example. The right pixel RP (m, n) is controlled by the thin film transistor M2, the gate of the thin film transistor M2 is electrically connected to the scan line Sm, and the first terminal of the thin film transistor M2 is electrically connected to the data line Dn. The left pixel LP (m, n) is controlled by the thin film transistor M11 and the thin film transistor M12. The gate of the thin film transistor M11 is electrically connected to the scan line Sm+1, while the source of the thin film transistor M11 is electrically connected to the data line Dn. The gate of the thin film transistor M12 is electrically connected to the scan line Sm, while the source of the thin film transistor M12 is electrically connected to the drain of the thin film transistor M11.
Referring to FIG. 4, a timing diagram of the scan signals of the scan lines Sm, Sm+1 and Sm+2 of the circuit of FIG. 3 is shown. The scanning of the pixels in each row can be divided into two phases of sub-scanning. The first sub-scanning scans all left pixels LP in a row, while the second sub-scanning scans all right pixels RP in the row. For example, when the pixels in the mth row are scanned, at first, during a first time period T1, the scan lines Sm and Sm+1, are enabled at the same time, meanwhile, the thin film transistors M11 and M12 are turned on at the same time, so a pixel voltage is inputted to the left pixel LP (m, n) via the data line Dn. Then, during a second time period T2, only the scan line Sm is enabled in the second phase of sub-scanning, meanwhile, the thin film transistor M2 is turned on, so a pixel voltage is inputted to the right pixel RP (m, n) via the data line Dn.
In the conventional practice disclosed above, the enabled time of the scan lines Sm and Sm+1 during a first time period T1 is equivalent to the enabled time of the scan line Sm during a second time period T2. Therefore, the charge time of the left pixel LP (m, n) is equal to the charge time of the right pixel RP (m, n).
In the liquid crystal display panel disclosed above, every two adjacent pixels in the same row share the same data line. The liquid crystal display panel disclosed above enables a data line to charge two adjacent pixels in the same row by different scan control signals transmitted by serially connected thin film transistors. When the data line charges the pixel electrode of the left pixel LP having dual thin film transistors, the data line signal has to pass through two thin film transistors, so the current charged to the left pixel LP is smaller than the current charged to the right pixel RP. Consequently, the charge ability of the left pixel LP is inferior to the charge ability of the right pixel RP. Thus, when the driving method of FIG. 4 is used, the left pixel LP will be under charged. As a result, proper luminance cannot be achieved, and the image quality of the display is affected.